Design and implementation of all-digital DLL and duty cycle corrector circuit
Date Issued
2007
Date
2007
Author(s)
Kao, Shao-Ku
DOI
en-US
Abstract
This thesis describes digital implemented the analog circuit with advanced standard sub-micro CMOS technology to solves of clock skew and duty cycle. The digital implemented IC can achieve a fine performance compare to the analog. It has high portability and scalability across different technology process. Its high integrity, low power, and low jitter performance can be easily incorporated into a single chip and successful realization of the system-on-a-chip (SOC). A clock with 50% duty cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore duty-cycle corrector (DCC) is needed to correct duty cycle as 50%.
This dissertation provides an all-digital pulsewidth control loop (PWCL) with adjustable duty cycle. The output clock is not only achieved 50% duty cycle, but can adjust from 30%~70% in steps of 10%. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle of input clock. Then, we proposed the PWCL is embedded with an all-digital delay-locked loop. Therefore, the output of clock can synchronize with input clock and also with variable duty cycle. Both experimental chips have been fabricated in a 0.35um CMOS process. The operation frequency range is from 400 MHz to 600 MHz.
Next, we develop all-digital duty cycle corrector circuit; the first test chip generates the 50% duty cycle and synchronizes with input clock. The measurement results shows the proposed circuit operates with input frequency range with 0.8~1.2GHz and input 40%~60% duty cycle. The second test chip, a period monitor is used to track the period of input to keep 50% duty cycle, when the period of input clock is changed. The proposed circuit works for the input duty cycle of 10%~90% and the measured operation frequency range is from 1 GHz to 1.6 GHz. The all-digital duty cycle corrector circuits have been verified on silicon using 0.18um CMOS technology.
Subjects
延遲鎖定迴路: 工作週期修正電路
delay locked loop: duty cycle corrector circuit
Type
thesis