A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
2015-July
Pages
553-556
Date Issued
2015
Author(s)
Abstract
An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closed-loop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm 2 .
SDGs
Type
conference paper