Insulating halos to boost planar NMOSFET performance
Journal
IEEE Transactions on Electron Devices
Journal Volume
57
Journal Issue
10
Pages
2526-2530
Date Issued
2010
Author(s)
Hsu, W.-W.
Lai, C.-Y.
Liu, C.W.
Ko, C.-H.
Kuan, T.-M.
Wang, T.-J.
Lee, W.-C.
Wann, C.H.
Abstract
Short-channel controllability by insulating halo (IH) is investigated using the NFET strained-Si technology. By embedding SiO 2 /Si 3 N 4 insulators in the halo regions, the increase of halo implant concentration reduces source/drain depths and improves short-channel effects such as drain-induced barrier lowering. With I off similar to the control device at the same gate length by adjusting the threshold voltage, the channel doping can be reduced, and the channel mobility increases due to the decrease of vertical electric field. Moreover, IHs reduce the shallow trench isolation compressive stress in the channel and yield a high-electron mobility enhancement. The device performance is optimized based on the simulation design. Up to a 23% I on improvement was experimentally achieved by optimal IH insertion. A 7% lower junction capacitance and an 8% ring oscillator speed improvement are demonstrated when the IH is adopted in the NFET alone. Moreover, device reliability is carefully examined and is not adversely impacted by IH insertion.
Type
journal article