Template-based Runtime Reconfiguration Scheduling for Partial Reconfigurable SoC.
Journal
13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea
Pages
542-549
Date Issued
2007
Author(s)
Chia, Li
Abstract
Reconfigurable hardware provides multiple functions without greatly increasing the die size of SoCs. Field Programmable Gate Array (FPGA), one type of reconfigurable hardware, is developing rapidly to handle high speed and complex applications. In particular, SRAM-based FPGA can be reconfigured during run-time to provide functionality as needed, thus reducing cost and power consumption. However, the reconfiguration delay time and limited resource on FPGA pose new challenges to many real-time scheduling applications. In order to optimize hardware usage and eliminate the impacts of reconfiguration delay, the scheduling algorithms and resource management mechanisms for reconfigurable SoC have to be re-designed. In this paper, we develop a template-based approach to reuse hardware resources without compromising the reconfiguration and performance constraint. The developed solution makes use of offline generated templates to generate near-optimal schedules during run-time. © 2007 IEEE.
Other Subjects
And real time; Complex applications; delay-time; Die size; Field programmable gate array (FPGA); Hardware resources; High speeds; In order; international conferences; multiple functions; Optimal scheduling; Performance constraints; Power consumption (CE); Re-configurable; Real time scheduling; Reconfigurable hardware (RH); Resource management (RM); Run time; Run time reconfiguration (RTR); SRAM based FPGA; to many; Computer systems; Embedded systems; Field programmable gate arrays (FPGA); Function evaluation; Information management; Knowledge management; Management; Production control; Programmable logic controllers; Resource allocation; Scheduling; Real time systems
Type
conference paper