Design and Phase Noise Analysis for Edge-Combining DLLs
Date Issued
2012
Date
2012
Author(s)
Liao, Fang-Ren
Abstract
In this dissertation, design issues such as output spur reduction, phase noise analysis, and delay mismatch calibration for edge-combining DLLs are discussed. The DLL-based frequency synthesizer outperforms its PLL counterpart by smaller chip area, less noise accumulation, and wider output range due to the frequency multiplication. However, the main problem associated with the edge-combining DLL, is output spur, which is caused by the static phase offset in the DLL loop and delay mismatches among delay cells in the VCDL. In Chapter 2, an edge-combining DLL is designed in a CMOS 90-nm process that can switch frequency fast and cover 0.45 to 5.4 GHz output frequency. The current-splitting CP is proposed to reduce the current mismatch during the idle interval of the PD so that output spur achieves 9.1 dB, 6.7 dB, and 15.4 dB improvement as compared to the current-steering CP for the frequency multiplication of 6, 3, and 2, respectively.
Despite lots of works focused on the implementation of the edge-combining DLL, almost no work provides phase noise analysis at the frequency-multiplied output in contrast to PLLs. Conventionally, the edge-combining DLL is categorized as a special case of phase-realigned PLLs (RPLLs) by assuming that the phase-shift factor, beta, is 1. The closed loop noise model for the RPLL is then used to explain the edge-combing DLL. However, since the output frequency of the edge-combining DLL can be varied by changing the edge combining sequence directly, output phase noise will differ if a different number of or different spacing between edge transitions are adopted. A modified phase-noise model is proposed in Chapter 3 by superimposing the noise jitter from the DLL on the periodic steady-state solution at the edge-combining output. The derived noise theory then discloses the fundamental difference between edge-combining DLLs and PLLs. The success of the proposed theory is verified even if the frequency multiplication factor changes.
Although output spur can be improved by reducing the static phase offset in the loop, delay mismatches among delay cells in the VCDL are also important problems. Delay mismatches can be traditionally calibrated by using relative phase comparison or absolute phase comparison. Due to the lack of a precise reference in the circuit, relative phase comparison is supposed to be more realizable than the absolute one. However, the main issue for the relative phase comparison is that the external phase comparators, required to compare the phase difference between the adjacently delayed outputs, introduce extra comparison mismatches. As for absolute phase comparison, the phase difference between the adjacent stages is calibrated to the same reference delay cell by using the same calibration path, eliminating the possible mismatches during phase comparison. Nevertheless, the accuracy of the reference delay cell is an issue. The deviation of the reference delay cell may cause the output phase of the feedback signal larger or smaller than 2*pi, even if the phase differences among the delay cells are the same. A prototype common calibration DLL is proposed in Chapter 4 to solve this issue.
Subjects
delay-locked loop (DLL)
edge combiner
frequency multiplier
spur
periodic steady state (PSS)
phase noise
mismatch calibration
Type
thesis
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