A 57–78 GHz frequency tripler MMIC in 65-nm CMOS
Journal
IEEE Microwave and Wireless Components Letters
Journal Volume
26
Journal Issue
9
Pages
68-81
Date Issued
2016
Author(s)
Abstract
In this letter, we present a MMIC frequency tripler using 65-nm CMOS technology. The tripler consists of a buffer stage that overdrives tripler devices into non-linear region, maximizing the third harmonic generation. Adopting differential architecture and transformers impedance matching, the tripler needs no explicit passive filter to enhance harmonic rejections. The tripler shows peak conversion gain of 1.3 dB, saturated output power of -2 dBm with -5 dBm input power. The 3-dB bandwidth spans 57-78 GHz with 60 mW dc consumption.
SDGs
Type
journal article