VLSI Architecture Design and Implementation of IF and Baseband Analog Front End. for Digital Multimedia Wireless Receiver (III)
Date Issued
2002-07-31
Date
2002-07-31
Author(s)
汪重光
DOI
902215E002044
Abstract
This report presents an analog front-end VLSI
architecture that deals with IF signal in wireless LAN
system. The center frequencies of RF and IF chosen are
2.4GHz and 280MHz respectively, and the baseband
bandwidth is 17.6MHz. The mixer, low pass filter, and
ring oscillator circuits are designed and post-simulated
in the third period. The implementation of whole IF
portion must be accomplished, and the chip must be
tested for verification. The last procedure is the
integration of RF and IF portions in this project. All
the circuits employ TSMC 0.35μm CMOS standard
technology using single power supply 3V. The chip of
IF/Baseband downconverter occupied area of
2.4mm2mm.
Subjects
limiting amplifier
received signal strength
indicator
indicator
wideband amplifier
bandpass filter
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
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Name
902215E002044.pdf
Size
1.56 MB
Format
Adobe PDF
Checksum
(MD5):011830e5bb0a7dab4c3a030eef4965da