Robust Transceiver Design for Full-duplex Multichannel Baseband Tomlinson-Harashima Precoded 10GBASE-T Systems

Multi-input multi-output (MIMO) techniques have been used to increase the data rate in high-speed communication systems. One of the successful applications is the 10GBASE-T system which is a full-duplex multichannel baseband system using Tomlinson-Harashima (TH) precoding (THP) techniques. The challenges to design a robust transceiver against the channel variation for 10GBASE-T are the channel-interdependence, loop-interaction and nonlinearity associated with the THP. Moreover, for the system with data transmission rate of 10Gbps, both the noise-margin and timing-margin become much tighter. Therefore, a robust design of equalization and timing recovery mechanisms is crucial and critical.n this dissertation, we analyze the impact of fixed-coefficient THP on the decision-point signal-to-noise ratio (DP-SNR) in the presence of imperfect channel state information (CSI) and propose a solution of the robust transceiver architecture which includes adaptive reception and multichannel symbol timing recovery (MC-STR) architectures. For adaptive reception, we propose an adaptive two-stage equalization and far-end crosstalk (FEXT) cancellation (TS-EFC) without updating the THP coefficients to combat the channel variation at both transmitter and receiver sides. In the first stage, we propose a new non-decision-directed FEXT canceller at the transmitter side to avoid error propagation. In the second stage, we devise an adaptive MIMO equalizer together with a novel pre-processing unit at the receiver side to combat the residual errors. For MC-STR systems, we propose a better scheme called the averaged-sampling-phase (ASP) which reduces the noise caused by an imperfect CSI and interference induced among multiple channels. Moreover, an associated three-phase timing strategy is also proposed to mitigate the loop-interaction and to extract correct timing error information during both training and data modes. In the data mode, we devise an effective data sequence based timing error detector (EDS-TED) which exploits the autocorrelation between EDS signals so that the embedded timing error information can be extracted out. Similar methodology can also be applied on non-loop-timed implementations. We discuss the loop delay concerns for the non-loop-timed implementation and propose a receiver architecture in which the loop delay is reduced at the price of adopting a more complicated asynchronous delayed least mean square (AD-LMS) algorithm for equalizer adaptations. imulation results show that our TS-EFC architecture is robust against to channel variation and significantly improves the DP-SNR. It eliminates the error propagation and also achieves faster convergence rate during adaptation process; moreover, the proposed ASP scheme reduces not only the timing jitter by 50% but also improves the DP-SNR by up to 1.40 dB in the presence of imperfect CSI on some channels of the multichannel; the proposed EDS-TED achieves the best performance, compared to the conventional TEDs, in terms of the resultant peak-to-peak jitter and TED gain.