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College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
Improving DRAM latency with dynamic asymmetric subarray
Details
Improving DRAM latency with dynamic asymmetric subarray
Journal
Annual International Symposium on Microarchitecture
Journal Volume
05-09-December-2015
Pages
255-266
Date Issued
2015
Author(s)
Lu, S.-L.
Lin, Y.-C.
CHIA-LIN YANG
DOI
10.1145/2830772.2830827
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-84959884230&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/392033
Type
conference paper
