GPS接收機之自動增益控制電路設計
Design of Automatic Gain Control Circuits for GPS Receiver
Date Issued
2005
Date
2005
Author(s)
Li, Kuan-I
DOI
zh-TW
Abstract
GPS system can cope with wideband noise or low power narrowband interference with the processing gain of spreading code. However, GPS system can not reject high power narrowband interference completely. Therefore, anti-jamming technique has become an important issue. This research proposed a frequency domain anti-jamming GPS receiver scheme. Considering the huge dynamic range of the system, the thesis proposed an automatic gain control system which has a dynamic range of 90dB and is of feedback type and mixed-signal type structure.
In order to maintain the performance of the anti-jamming device, the time interval of the adjustment of the AGC is synchronized with the FFT window. Moreover, the AGC sends its gain information to the anti-jamming device as the criterion of jamming excision.
The signal path in the AGC utilizes the chip AD8963 as the VGA and AD9244 as the ADC. The backward path is implemented with digital circuits. In order to reduce the circuits area and the power consumption, CSD and sub-expression sharing is introduced for digital filter coefficient representation. Moreover, the lowpass filter in the peak detection device is implemented with CIC structure which utilizes a few adders/subtracters to realize high order FIR filter. Furthermore, CIC register length pruning design is introduced to improve circuits efficiency.
With software simulation which emulates realistic conditions, the AGC is proven to meet the operation goal in environments with no jamming or in the occurrence of continuous wave interference (CWI), multi-tone CWI, swept CWI, and pulsed CWI. Afterwards, the digital circuits are designed and evaluated with Verilog language in SOPC development software and programmed to Altera StratixII FPGA board. Finally, the AGC hardware integration is completed and verified.
Subjects
自動增益控制
GPS抗干擾
Automatic Gain Control
GPS anti-jamming
Type
thesis
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