An 89.55dB-SFDR 179.6dB-FoMS 12-bit 1MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration
Journal
IEEE Asian Solid-State Circuit Conference
Pages
1月5日
Date Issued
2018
Author(s)
Abstract
This paper presents an 89.55dB-SFDR 2.55μW 12-bit lMS/s SAR-assisted SAR ADC in 40nm CMOS at a 0.7V supply. The proposed weight-split compensation provides an accurate mapping between capacitor mismatch and digital weight to take advantages of both low-power skipping switching method and robust digital calibration. The reconfigurable redundancy region with tracking bits is used to speed up the calibration time to only 112 clock cycles. The SFDR is improved by 19.45dB with unit capacitors of 0.25fF for power-saving. The prototype ADC achieves an SNDR of 69.1 dB at Nyquist rate. It results in an FoMs of 179.6dB and an FoMw of 1.43fJ/c.-s.
SDGs
Type
conference paper