VLSI Architecture Design and Implementation of IF and Baseband Analog Front End. for Digital Multimedia Wireless Receiver (I)
Date Issued
2000-07-31
Date
2000-07-31
Author(s)
汪重光
DOI
892215E002025
Abstract
This report proposes an analog front-end VLSI
architecture that deals with IF signal in wireless LAN
system. The frequencies of RF, IF and baseband
chosen are 2.4GHz, 280MHz and 17.6MHz
respectively. Low-power high-speed analog front-end
architectures and circuits of limiting amplifier, RSSI
(Received Signal Strength Indicator), and IF/Baseband
down-converter were investigated and designed in the
first period. Using 0.35μm CMOS standard
technology, the limiting amplifier which is used to
provide constant magnitude achieves 80dB gain with
290MHz bandwidth, and the RSSI compasses 40dB
dynamic range with 3dB error performance.
Subjects
limiting amplifier
received signal strength
indicator
indicator
wideband amplifier
bandpass filter
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
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892215E002025.pdf
Size
379.62 KB
Format
Adobe PDF
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(MD5):841266afca276ae05e6a00aa98c2a1e8