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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design
Details
Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design
Date Issued
1985
Date
1985
Author(s)
Feng, Wu-Shiung
URI
http://ntur.lib.ntu.edu.tw//handle/246246/106210
Type
report