A 40-nV/√Hz 0.0145-mm2 Sensor Readout Circuit with Chopped VCO-based CTDSM in 40-nm CMOS
Journal
IEEE A-SSCC
Date Issued
2016
Author(s)
Abstract
A sensor readout circuit employing chopped VCO-based CTDSM is presented in this paper. This VCO-based ADC features direct connection to the sensors to eliminate pre-amplifier. The VCO is designed as a Gm-CCO, which is a G m stage cascaded with the folded-cascode current-controlled oscillator. The proposed circuit ensures a high input impedance. Furthermore, the main noise and offset contributor, the Gm stage, is mitigated by chopping operation. The VCO-based CTDSM is implemented in 40-nm CMOS. The whole circuit draws 14 μA from 1.2-V supply. With a 2.4-mVpp input, it achieves 49.43 dB SNDR over 5-kHz BW and has SFDR of 59.5 dB. The input-referred noise is 40nV/√Hz. The chip area is only 0.0145 mm 2 .
SDGs
Type
conference paper