All-digital fast-locked synchronous duty cycle corrector
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
53
Journal Issue
12
Pages
1363-1367
Date Issued
2006-12
Author(s)
Shao-Ku Kao
Abstract
An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18- μ m CMOS technology. The measured duty-cycle error is between 1.5% and —1.4% for the input duty cycle of 40% ~ 60%. The measured peak-to-peak jitter is 12.9 ps at 1 GHz. The measured operation frequency range is from 0.8 GHz to 1.2 GHz. © 2006, IEEE. All rights reserved.
Subjects
All-digital; duty-cycle corrector (DCC); fast-locked
Other Subjects
Jitter; Networks (circuits); Synchronization; All-digital fast-locked synchronous duty-cycle corrector; Duty-cycle error; CMOS integrated circuits
Type
journal article