Multilayer Bus Minimization Problems for SoC Systems
Date Issued
2008
Date
2008
Author(s)
Tsai, Hsin-Liang
Abstract
The deployment of multiple processing elements, such as a microprocessor or DSP''s, in embedded systems often result in significant communication overheads. How to resolve the communication problems and, at the same time, satisfy the timing constraints in job executions is very challenging. In this paper, we explore multi-layer bus minimization problems by identifying factors that contribute to NP-hardness of the problems. We first present problems with efficient algorithms and then NP-Hard problems. A simulated annealing algorithm is also proposed to serve as a comparison with heuristics-based algorithm to provide insights in system designs. A series of extensive simulation experiments and a case study are presented to provide insights and comparisons among different approaches.
Subjects
embedded system
on-chip bus
multi-layer bus
bus minimization
simulated annealing
Type
thesis
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