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  4. Design and Implementation of Reconfigurable Communication Engine
 
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Design and Implementation of Reconfigurable Communication Engine

Date Issued
2003-07-31
Date
2003-07-31
Author(s)
吳安宇  
DOI
912215E002044
URI
http://ntur.lib.ntu.edu.tw//handle/246246/19988
Abstract
With the advent of the 2G/2.5G/3G high-speed telecommunication, the communication system of multi-standard / multi-mode and the multi-mode in single standard has become a trend as to offer a variety of communication services. On the one hand, DSP (Digital Signal Processing) is often the solution to the design of communication ICs at present. The processing speed of most DSP, however, is not fast enough to handle the great deal of transmitted data in high-speed telecommunication systems. On the other hand, the ASIC designs, in general, can not dynamically adjust the function of modules to maintain the required performance. When the specifications of the system change, it will take a lot of costs and time to redesign the IC circuits. In the project, we propose a novel architecture of communication system to achieve the best balance between the design cost and the functions of transceiver. This architecture is called Reconfigurable Communication Engine (RCE), which can dynamically adjust the functions of modules to meet the altered specifications of the system. We plan to adopt the commonly used modules in communication systems, such as Viterbi decoder, Reed Solomon encoder/decoder, and Fast Fourier Transform (FFT) processor. We will make a detail analysis at algorithm level to reduce the complexity. There are two main cores in each module, including Hardcore and Softcore. The Data path is fixed in the hardcore so that the area, processing speed, and power consumption of modules are expectable and controllable. The conception of the reconfigurable computing is introduced in the softcore design. According to the change of system specifications, we can dynamically adjust the hardcore of modules by controller so as to meet the system requirement. The target design has the property of high speed, low power consumption, scalability, and portability.
Publisher
臺北市:國立臺灣大學電子工程學研究所
Type
report
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