Atomic Scale Modeling and Simulation of the Gate Dielectrics (I)
Date Issued
2003-07-31
Date
2003-07-31
Author(s)
楊照彥
DOI
912212E002059
Abstract
The rapid scaling of -Sbiased CMOS devices has led to silicoino xdide gate
insulating film less than 2.-0nm thick. By year 2008, the -7n0m generation needs
alternative gate dielectric material with higher K value than that of silicon dioxide.
Traditional TCAD tool is not sufficient and atomic scale modeling and simulation is
needed for the IC design and analysis. In first year (I), we have carried out the
molecular dynamics simulation using empirical interatomic potential and tight
binding theory to study the thin-film deposition. PC cluster tool is established for
parallel implementation. The results indicate that the computational environment
and simulation model and code have been completed and provide the basis for next
stage quantum modeling/DFT simulation.
Publisher
臺北市：國立臺灣大學應用力學研究所
Type
report
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