Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits
Journal
IEEE Asian Test Symposium
Date Issued
2009-01
Author(s)
Abstract
This poster presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin-film (a-Si TFT) transistor technology as an economic alternative to burn-in. A total number of 140 CUT implemented in 8¿m a-Si TFT technology are tested at nominal voltage and very-low-voltage. The results indicate that VLV testing is effective in screening out unreliable a-Si TFT circuits.
Type
conference paper