A SAR-assisted continuous-time incremental �m�_ adc with first-order noise coupling
Journal
Proceedings of International Conference on ASIC
Date Issued
2019
Author(s)
Hsieh, Y.-L.
Abstract
A 25-kHz 3rd-order continuous-time incremental sigma-delta modulator is proposed by utilizing a 5-bit successive-approximation-register (SAR) quantizer, incorporating 1st-order noise coupling (NC) and excess-loop-delay compensation (ELDC) into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). This prototype fabricated in a TSMC 40 nm LP CMOS technology measures a peak 71.98 dB SNDR at an over-sampling ratio (OSR) of 32, yielding a Schreier FoM of 160.5 dB and a Walden FoM of 1.39 p.J/conversion-step. The modulator occupies an active area smaller than 0.32 mm 2 and consumes 225 μW.
SDGs
Type
conference paper