An efficient linear-phase FIR filter architecture design for wireless embedded system
Resource
Signal Processing Systems, 2001 IEEE Workshop on
Journal
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Pages
193-200
Date Issued
2001
Author(s)
Abstract
This paper presents a novel approach for implementing power-efficient finite impulse response (FIR) filters that require less power consumption than traditional FIR filter implementations in wireless embedded systems. The proposed schemes impose to the direct form and achieve a certain reduction in the power consumption. A novel retimed structure and balanced modularized techniques are introduced and used to reduce the critical path to achieve hardware efficiency. A novel separated signed processing data flow scheme with modifying CSD (canonical signed digit) representation is also introduced and used to reduce the transition, which is the main source of power consumption. The combination of the proposed methods gives up to 71% reduction in power consumption with a slight area overhead.
SDGs
Type
conference paper
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