OpenCL Computing on FPGA Using Multiported Shared Memory
Date Issued
2014
Date
2014
Author(s)
Mutlugün, Tahsin Türker
Abstract
High-Level Synthesis (HLS) targeting FPGAs has been widely used for high performance computing. With the introduction of OpenCL, some of the HLS research have shifted towards bringing OpenCL to FPGAs. This thesis presents an OpenCL architecture for FPGAs and focuses on memory access improvements with the goal of achieving optimal performance. In OpenCL compute blocks, there is usually a linear relation between computation time and local memory access latency. This latency is normally hidden by increas- ing the parallel workload. However, with such an approach, target FPGA device could easily run out of resources. In this work, conflict-free multi- ported memories have been used instead to minimize local memory access latency. Experiments show that multiported memories can successfully increase computation speed and reduce the required parallel workload for max- imum throughput to practical amounts.
Subjects
OpenCL
課程式陣列邏輯
多埠記憶體
高級綜合
SDGs
Type
thesis
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