Design and Implementation of Clock and Data Recovery Circuit
Date Issued
2006
Date
2006
Author(s)
Yang, Zong-Jin
DOI
en-US
Abstract
With the growing demand on transmission rate, the serial data communication has evolved into tens of gigabits per second for wide area network and the backbones. Optical communication system will be a mainstream in the future, and Ethernet plays an important role in such high speed network. Clock and data recovery circuit (CDR) is the most complicated component of it. We use TSMC 0.18μm 1P6M CMOS technology to implement this high speed circuit to achieve low cost, low power consumption, and highly integrated capability.
This thesis focuses on the design of clock and data recovery circuit in OC-192 system. We design a new voltage controlled oscillator which can reduce phase noise, and make better jitter performance of whole circuit. The recovery clock exhibits a peak to peak jitter of 1.65ps for a PRBS sequence of length 215-1. The CDR circuit dissipates a total power of 105mW with a 1.8V supply and occupies a die area of 0.75 mm x 0.75 mm.
Subjects
時脈與資料回復
Clock and data recovery
CDR
Type
thesis
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