A 10-GHz CMOS PLL with an Agile VCO Calibration
Journal
IEEE Asian Solid-State Circuit Conference
Pages
213-216
Date Issued
2005-11
Author(s)
Y.-J. Lai
Abstract
This paper reports a fully-integrated 10-GHz CMOS PLL with an agile VCO frequency calibration circuit. The proposed method automatically searches for the optimum VCO tuning curve out of a band of curves using much less time than other existing approaches. The agility is due to the novel searching technique which is based on the comparison of signal periods, rather than counting signal cycles or reading the VCO control voltage after the PLL settled. The proposed PLL is implemented in a 0.18-mum CMOS process. The measured PLL output phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are below -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4 musec
SDGs
Type
conference paper