A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques
Journal
IEEE Transactions on Circuits and Systems, Part I
Journal Volume
58
Journal Issue
6
Pages
1157-1166
Date Issued
2011-06
Author(s)
Y-C Huang
Abstract
A 10-bit pipelined ADC employs both opamp-and time-sharing techniques to reduce the power consumption and silicon area. The proposed ADC needs only one opamp to complete the 10-bit conversion. This ADC has been fabricated in a 90-nm digital CMOS technology and occupies only 0.058 mm 2 . It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0-V supply.
SDGs
Type
journal article