The Interconnect Fringing Capacitance Model and Its Applications to the Study of Pull-in Voltage of Micro Devices
Date Issued
2008
Date
2008
Author(s)
Wang, Chang-Wen
Abstract
This research aims at developing empirical formulas for parallel-plate capacitor precisely, including two- and three-dimensional fringing capacitance effects. The derivation was started from massive numerical simulations of different geometry, and then we can derive two- and three- dimensional fringing capacitance formulas from choosing appropriate parameters to curve-fitting on results obtained from simulations. The relative errors of two- and three-dimensional fringing capacitance formulas are within 2 and 4 percent comparing with numerical simulations, respectively. Next, we derived the pull-in voltage of micro-devices from these formulas and it shows very high accuracy comparing with experimental data obtained from literature. It demonstrates that the formulas we proposed can apply to the design of microelectromechanical devices. Finally, in order to verify these formulas we proposed actually, we conducted experiment of two- and three-dimensional fringing capacitance by the semiconductor processing. The relative errors of two- and three-dimensional fringing capacitance formulas are within 3 and 5 percent comparing with experimental data, respectively. These high precision empirical formulas are more convenient than other proposed methods, and the accuracy, the applicative range, and the physical meaning are better, too. Therefore, by these high precision formulas, designers can easily evaluate the capacitance through the geometry in a few seconds.
Subjects
Capacitance
Parallel-plate Capacitor
Fringing Capacitance
Micro-device
Pull-in Voltage
Microelectromechanical
MEMS
Type
thesis
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