Design and Implementation of Fully-Differential Comparator-Based Switched-Capacitor Analog-to-Digital Converters
Date Issued
2008
Date
2008
Author(s)
Huang, Mu-Chen
Abstract
A comparator-based switched-capacitor (CBSC) circuit topology published recently was introduced to substitute conventional op-amp-based designs in pipelined ADCs. The general concept of CBSC technique is to replace an op-amp with a threshold-detection comparator which is able to detect virtual ground condition rather than forcing it. The original CBSC prototype is realized with a singled-ended pipelined ADC. Nevertheless, for better rejection of supply and substrate noise, fully-differential circuit architecture is indispensable in modern mixed-signal integrated circuits where the di/dt noise from the digital circuits may be a severe problem to the analog parts on the same chip.o address the above issue, fully-differential comparator-based switched- capacitor (CBSC) circuits are proposed in this thesis. A 2.56MS/s second-order delta-sigma (ΔΣ) and a 10MS/s to 2kS/s power-scalable 10-bit pipelined ADC with self-adjusted current scaling have been realized with the presented techniques. By using the proposed fully-differential CBSC integrators and common-mode feedback circuits, the prototype second-order ΣΔ modulator achieves 65.3dB SNDR and an input dynamic range of 71dB within the signal bandwidth of 20 kHz, which corresponds to an oversampling ratio of 64. The active area of the ΣΔ modulator is 0.21mm2, while the power consumption excluding output buffers is 0.42mW at 1.8V.o realize the power-scalable CBSC pipelined ADC, a self-adjusted current scaling (SACS) method is presented to enhance linearity and SNDR when decreasing the sampling rate. Experimental results show that the ADC achieves 53.3dB SNDR and 62.3dB SFDR while sampled at 10MS/s and consuming 1.95mW from a 1.8V supply, which obtains a figure-of-merit (FOM) of 510fJ/step. In addition, when the sampling rate gradually reduces from 10MS/s to 2kS/s, the peak SNDR increases from 53.3dB to 56.6dB at most, and is constantly 2-3dB higher than the situation when SACS is disabled. Finally, the power consumption as the operating frequency goes down continuously decreases from 1.95mW (10MS/s) to 131.5μW (2kS/s), validating the power scalability of the prototype ADC.
Subjects
Analog-to-digital converter
Delta-sigma modulator
Pipelined ADC
Comparator-Based Switched-Capacitor
CBSC
Type
thesis
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