A Fractional-N Frequency Synthesizer with Noise-Filtering Technique
Date Issued
2014
Date
2014
Author(s)
Liao, Kun-Hsun
Abstract
The raw performance of wireless communication system primarily hinges upon that of their constituent frequency synthesizers. The phase noise requirement and channel bandwidth limitations for wireless communication standards underline the consequence of fractional-N frequency synthesizer. The phase noise performances of fractional-N frequency synthesizer imposed by the quantization noise have motivated various noise-cancelling techniques that afford the use of low phase noise fractional-N frequency synthesizer in modern wireless devices.
This thesis explores the notion of quantization noise cancellation technique in the design of fractional-N frequency synthesizer and introduces the proposed noise-filtering technique with an overview of wireless communication system. In chapter 2, a noise-filtering technique to suppress the quantization noise of a 3.6GHz fractional-N frequency synthesizer is realized in a 40-nm CMOS technology. The injection-locked oscillator (ILO) incorporated with digital calibration circuits are implemented as a noise filter to cancel quantization noise.
The active area and power consumption of noise filter with calibration circuit are 0.0067 mm2 and 0.1mW, respectively. It is shown that the ILO based noise filter offers significant advantages over the previous arts in area and power consumption issues. Analysis of the noise filter model is present and demonstrates its low-pass characteristic. The circuit description and the corresponding design issues are also analyzed and discussed. Finally, the experiment results show that the proposed architecture achieves 9.95dB quantization noise suppression at 10MHz frequency offset and the root-mean-square (RMS) jitter can be improved from 3.57ps to 2.56ps.
Subjects
量化雜訊
頻率合成器
Type
thesis
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