Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect
Resource
Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003. The 11th IEEE International Symposium on
Journal
The 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003.
Pages
-
Date Issued
2003-11
Date
2003-11
Author(s)
Kuo, J.B.
Sun, E.C.
Lin, M.T.
DOI
N/A
Abstract
This paper reports an analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted (FD) silicon on insulator (SOI) NMOS devices using a compact model considering fringing electric field effect. Using the conformal mapping transformation approach, a closed-form compact model considering the fringing electric filed effect above the non-gate overlap region has been derived to provide an accurate prediction of the threshold voltage behavior as verified by the 2D simulation results.
Type
journal article
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