Toward On-the-fly Reconfigurable FPGA Applications by Efficient SAT-Based Logic Rectification Techniques
Date Issued
2012
Date
2012
Author(s)
Huang, Po-Kai
Abstract
On-the-fly partial reconfiguration on FPGA designs has become an increasingly im-portant requirement in recent years. With this attribute, the behavior of a system can be changed partially while the rest of the design is still preserved. It is especially useful for applications in such as military or communication devices which require flexible and adaptive hardware. However, there are limited supports and automation in design tools to generate appropriate modifications for partial reconfiguration. Moreover, when there are significant numbers of modifications, it is impractical and inefficient for users to derive the desired functions in a manual way. In this thesis, we propose an efficient automated flow which is able to search for the portions of the device needed for consideration and generate proper modifications for the reconfiguration. To be precise, our algorithm achieves the desired functionalities by only reconfiguring some of the Look-Up Tables (LUTs) while preserving engineering efforts on cell interconnections and placement. In addition, we develop several techniques to alleviate the complexity and improve the performance of the reconfiguration process. The experimental results show that our algorithm can achieve the reconfiguration of various targeted functions in both the logic and Register-Transfer (RT) levels efficiently and effectively.
Subjects
Error diagnosis
Logic rectification
Boolean satisfiability
FPGA
Type
thesis
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