A 3mW 12b 10MS/s sub-range SAR ADC
Journal
2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages
153-156
Date Issued
2009
Author(s)
Abstract
This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm 2 .
SDGs
Type
conference paper