A 8-bit 140MS/s pipelined ADC using folded sample-and-hold stage
Journal
International Conference on Electron Devices and Solid-State Circuits (EDSSC)
Pages
357-360
Date Issued
2007-12
Author(s)
Hwei-Yu Lee
Abstract
A 1.5-bit/stage 8-bit 140MS/s pipelined ADC with folded sampled-and-hold stage is presented. The proposed technique improves the nonlinearity without using complicated calibration circuitry and neither does it require extra calibration cycle. Only 17 comparators are required for a 5-bit flash ADC. This 8-bit pipelined ADC has been fabricated in a 0.18um CMOS process. It dissipates 39mW with a supply voltage of 1.8V and occupies 0.71mm 2 active area. The measured signal to noise plus distortion ratio (SNDR) is 46.4 dB at sampling rate of 140 MS/s. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.47-LSB and 0.86 -LSB, respectively.
A 1.5-bit/stage 8-bit 140MS/s pipelined ADC with folded sampled-and-hold stage is presented. The proposed technique improves the nonlinearity without using complicated calibration circuitry and neither does it require extra calibration cycle. Only 17 comparators are required for a 5-bit flash ADC. This 8-bit pipelined ADC has been fabricated in a 0.18um CMOS process. It dissipates 39mW with a supply voltage of 1.8V and occupies 0.71mm 2 active area. The measured signal to noise plus distortion ratio (SNDR) is 46.4 dB at sampling rate of 140 MS/s. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.47-LSB and 0.86 -LSB, respectively.
SDGs
Type
conference paper