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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
A 8-bit 140MS/s pipelined ADC using folded sample-and-hold stage
Details
A 8-bit 140MS/s pipelined ADC using folded sample-and-hold stage
Journal
International Conference on Electron Devices and Solid-State Circuits (EDSSC)
Pages
357-360
Date Issued
2007-12
Author(s)
Hwei-Yu Lee
SHEN-IUAN LIU
DOI
10.1109/EDSSC.2007.4450136
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/333746
SDGs
[SDGs]SDG7
Type
conference paper
