Design of CMOS Drain Mixers
Date Issued
2012
Date
2012
Author(s)
Yang, Hong-Yuan
Abstract
The purpose of this dissertation is to discuss the operation principles, circuit optimizations, and applicability of the CMOS passive drain-pumped mixer topology.
With the trend of wireless networks toward multigigabits transmissions, the millimeter-wave (MMW) band with ultra-broad bandwidth has become one of the major players for future gigabit-wireless transmissions. It also motivates the researches on MMW communication systems. For the modern receiver building blocks, a mixer with good conversion efficiency and low dc power is important. As a result, the passive mixer is one of the candidates for low-power applications. However, the high conversion loss of passive mixers is a serious drawback. Recently, a CMOS passive drain mixer with good conversion efficiency has been reported. This dissertation is to analyze the characteristics of CMOS drain mixers and to implement passive drain-pumped topology using innovative architectures.
We begin with the operation principles of a CMOS drain mixer. According to the simulation results of the bias tuning parameters and the time-varying output IF current, the relations between the gate bias and the conversion loss of the mixer are obtained. Using Taylor’s series analysis, a gate bias optimization method for the CMOS drain mixer design is proposed. The analytic formula can predict the optimum gate bias point, which agrees well with the circuit simulation data. It also simplifies the complexities of the CMOS drain mixer design flow.
To enhance the operation bandwidth of the CMOS drain mixer, we proposed a distributed drain-pumped topology. For the broad bandwidth and the conversion efficiency, the gate line and the drain line of the distributed mixer is analyzed to determine the gate inductances, drain inductances, device sizes and the number of stage. According to the wideband matching characteristics of distributed mixers, we utilize the mixer to discuss the differences between resistive mixers and passive drain mixers. Based on the experimental results, the design tradeoffs and differences of two mixers’ configurations are describes.
Since the conversion efficiency and the operation bandwidth of the CMOS passive drain-pumped topology have been investigated through the distributed architecture, we proposed another CMOS drain mixer using the doubly balanced architecture for the receiver applications. With the symmetric configuration of the doubly balanced architecture, the proposed mixer overcomes the port-to-port isolations limitation in the other single-stage CMOS drain mixer. In addition, a concept of impedance transformations using a Marchand balun network is described and successfully implemented in the mixer design. As compared to the reported resistive mixer topologies, like ring mixers and star mixers, the proposed doubly balanced drain mixer improves the conversion loss with a compact chip size, wide IF frequency selections and a moderate LO power requirement.
Subjects
mixer
MMIC
RF
Type
thesis
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