A V-band CMOS frequency quadrupler with 3-dBm output power
Journal
Asia-Pacific Microwave Conference Proceedings, APMC
Pages
199-201
ISBN (of the container)
978-145771330-9
Date Issued
2012
Author(s)
Abstract
A V-band frequency quadrupler implemented in 90-nm LP CMOS process is proposed with 3-dBm output power. This frequency quadrupler consists of a 30-GHz frequency doubler, a 30-GHz buffer amplifier and a 60-GHz frequency doubler. The measured maximum conversion gain is 3 dB at 66 GHz, and the 3-dB bandwidth is from 62 to 70 GHz under 0-dBm input drive power. Harmonic suppressions of the fundamental, the second and the third harmonics are all better than 30 dB. The dc power consumption is 53.4 mW, and the chip size is 0.57 × 0.59 mm 2.
Event(s)
2012 Asia-Pacific Microwave Conference, APMC 2012
Subjects
CMOS
doubler
quadrupler
V-band
SDGs
Type
conference paper