Implementation of High-resolution Multi-channel Time-to-digital Converter in FPGA
Date Issued
2015
Date
2015
Author(s)
Hsu, Ling-Yun
Abstract
FPGA-based TDC (Time-to-Digital Converter) provides a relatively low cost and flexible solution that incurs no non-recurring engineering and manufacturing delay. A high resolution FPGA-based multi-channel time-to-digital converter architecture is proposed in this thesis. In the proposed multi-channel TDC, a programmable latency is added before each TDC channel. This not only enhances ultra-wide bins sub-division between the channels, but also extends the measurement dynamic range with low area overhead. Calibration process with the proposed bin-merging algorithm is applied to re-arrange bin widths to achieve high accuracy for single-shot and repeatable events. The proposed TDC is realized on a Xilinx Spartan 6 development board DE-0630-00achievies. It achieves 40-ps resolution and 5.05-ns dynamic range with maximum INL/DNL less than 0.5 LSB. Furthermore, the proposed TDC consumes only 1% of FPGA logic elements (134 slices out of a total of 62,664 slices) and consumes 65 mW.
Subjects
time-to-digital converter
multi-channel
sub-division
FPGA
Type
thesis
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ntu-104-R02943083-1.pdf
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