A low power high accuracy CMOS time-to-digital converter
Resource
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Journal
Circuits and Systems, 1997. ISCAS '97.
Pages
-
Date Issued
1997-06
Date
1997-06
Author(s)
Chen, Poki
Liu, Shepz-Iuan
Wu, Jingshown
DOI
N/A
Abstract
In this paper, we present a new CMOS time-to-digital converter (TDC) with the cyclic delay line structure. The static supply current is 2-nA only. Furthermore, the continuous calibration is no longer needed. The TDC can be shunted down between measurements to make the power consumption negligible. The circuit with 64-stage cyclic delay line has been fitted into 0.25 mm/spl times/0.75 mm chip area with a typical 0.8-/spl mu/m SPDM process. The measured resolution is 286 picoseconds, and the measured single-shot accuracy is less than 143 picoseconds. Both can be made much less if the control voltage is well tuned.
SDGs
Type
journal article
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