An Exploration of Power Efficient Digital VLSI Design Techniques
Date Issued
2009
Date
2009
Author(s)
Cheng, Chih-Chi
Abstract
Reducing power consumption while meeting the throughput requirement has been important in designing a VLSI for most, if not all, applications. We think most power efficient VLSI design techniques can be classified into the following three categories: power optimization of signal processing circuits, on-chip memory power reduction techniques and off-chip memory power reduction techniques.n this thesis, those power efficient VLSI design techniques are explored with real design examples. Five chips are implemented and measured to verify the design techniques. The power optimization techniques for signal processing circuits have been thoroughly and systematically discussed in literatures. Therefore, we will lay stress on design techniques for off-chip memory power reduction techniques and on-chip memory power reduction techniques.hree design techniques about off-chip memory access reduction are discussed. According to the data reported by TOSHIBA, the power consumption of off-chip memory access occupies more than 67\% of the total power consumption in a portable multimedia recording system. We discussed three techniques to reduce off-chip memory access: embedded compression, on-chip data reuse, and SoC integration. Three design examples are provided. A multi-mode embedded compression codec chip reduces 62\% of off-chip memory power in video coding systems; an update-step engine in a scalable video encoder reduces 61\% of off-chip memory power by combining different on-chip data reuse schemes; iVisual intelligent visual sensor SoC eliminates all off-chip pixel data traffic by use of an SoC architecture.nother three design techniques for on-chip memory power reduction are discussed, and they are on-chip memory bit-width requirement analysis, on-chip memory hierarchy design, and lifetime reduction of intermediate data. There are four design examples shown in this part. A bit-width analysis methodology for multi-level 2-D discrete wavelet transform (DWT) provides a tight upper bound for dynamic range and an accurate round-off error analysis with 0.1dB PSNR prediction error; multiple-lifting 2-D DWT scheme reduces 78\% of SRAM power with an on-chip memory hierarchy scheme; the memory hierarchy design of iVisual also reduces 62\% of total power consumption; a level-switching DWT scheme for JPEG 2000 codec reduces 95\% of SRAM power by reducing the intermediate data lifetime.n brief, we explore, design, and implement a series of power efficient VLSI design techniques. Hopefully, through the systematic discussion, this thesis can bring some helpful information to designers.
Subjects
VLSI
SIMD
Recognition
Video Coding
Multimedia
Type
thesis
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