A Hardware Architecture Design of the Low-Density Parity-Check Code Decoder for IEEE 802.11n Standard
Date Issued
2012
Date
2012
Author(s)
Tung, Bo-Wen
Abstract
One of the main challenges of implementing an LDPC code decoder is that the interconnection
complexity is growing along with the number of the parallel processing
units, which results in the increased delay, power dissipation, and chip area. In this
thesis, we propose a design called split-core architecture with reduced-quantization method which reserves the benefit of split-row threshold algorithm proposed by Mohsenin and simultaneously retains the good error performance for a multi-mode LDPC decoder of 802.11n standard. The implementation results show that the area of a decoder with our proposed architecture is 2.58 mm2 with a final core utilization of 85%, as compared to the area of 3 mm2 and a core utilization of 70% for the non-splitting architecture, while the area sizes are similar for both architectures before the routing process.
Subjects
low-density parity check code
min-sum algorithm
permuted accelerated decoding
split-row threshold algorithm
routing congestion reduction
Type
thesis
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