Design of A High-Speed Pipelined A/D Converter with Open-Loop Amplifiers
Date Issued
2007
Date
2007
Author(s)
Shen, Ding-Lan
DOI
en-US
Abstract
Analog-to-Digital Converters (ADCs) are the key components which connect the real world with the discrete-computation fields. High-speed and low-resolution ADCs are wildly applied at the front end of high-performance serial-link systems. In this dissertation, replacing open-loop amplifiers with closed-loop amplifiers in the pipelined ADC are proposed to break through the speed limitation of pipelined architecture. The designed 6-b 800-MS/s pipelined A/D converter achieves SNDR and SFDR of 33.7dB and 47.5dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global-gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design trade-offs between speed and power. Fabricated in a 0.18-um CMOS technology, the ADC consumes 105mW from a 1.8-V power supply while the active area is only 0.5mm2. The linear approximation technique of the digital background calibration is proposed to enhance the resolution of the pipelined ADC with open-loop amplifiers in the end.
Subjects
類比數位轉換
管線式類比數位轉換器
積體電路
開迴路放大器
增益控制
數位背景校正
Analog-digital conversion
pipelined A/D converters
integrated circuits
open-loop amplifiers
gain control
digital background calibration
Type
thesis