System-Level Synthesis Algorithms for Real-Time SoC Design
Date Issued
2006
Date
2006
Author(s)
Chen, Yi-An
DOI
en-US
Abstract
System-on-a-Chips are usually synthesized by a number of ASICs, IPs, and (customized or general) microprocessors to reduce design overhead and manufacture cost. Which processing elements are chosen and how the chosen processing elements are assigned to complete the tasks have significant impacts on the cost and performance of the system. As the complexity of SoC increases, how to find an optimal system-level system architecture has became a critical issue for SoC design. Earlier researches focus on the system synthesis on operation level. In this thesis, we are concerned with system synthesis on system-level. The algorithms in this thesis determine the scheduling, allocating, and mapping on system-level. We compare the performance of several types of synthesis algorithms including exponential optimal algorithms, iterative heuristic algorithms, constructive heuristic algorithms, genetic-based algorithms. We shall present their performance for different task models. The result shows that the iterative heuristic algorithms can get the near optimal solution when there are not large number
of instances. As the number of instances increases, the genetic algorithm outperforms the other algorithms on cost, and its mean run-time overhead is still acceptable.
Subjects
即時
單晶片
排程
軟硬體協同設計
real-time
SoC
scheduling
synthesis
system-level
Type
thesis
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