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  4. Retention-Aware Read Acceleration Strategy for LDPC-based NAND Flash Memory
 
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Retention-Aware Read Acceleration Strategy for LDPC-based NAND Flash Memory

Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Date Issued
2023-01-01
Author(s)
Wang, Tse Yuan
Tsao, Che Wei
Chang, Yuan Hao
TEI-WEI KUO  
DOI
10.1109/TCAD.2023.3289328
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/634872
URL
https://api.elsevier.com/content/abstract/scopus_id/85163790538
Abstract
With the strong demand for stable and great quality of service in many network and multimedia services, flash-memory storage systems have been widely adopted in the storage I/O stack in servers and data centers to provide greater access performance. In these services, a huge-size storage system is essential. However, the huge-size flash storage system is very expensive. Flash storage vendors gradually adopt the high-density, low-reliability, and cost-efficient MLC NAND flash memory chip as the major storage medium. Unfortunately, MLC NAND flash memory also brings about the critical issue of the high raw bit error rate. To resolve this issue, vendors adopt the more complex error correction code (such as LDPC). However, LDPC also results in significant read performance degradation due to its multiple read-retry sensing and decoding steps. To resolve this issue, we proposed a retention-aware read acceleration design (referred to as RRA) for the LDPC-based flash storage system to maintain stable and great read performance without significantly affecting the lifetime. Without significantly modifying the existing FTL design, we proposed a retention-aware management module to the existing FTL design. This module can efficiently identify and predict the data access characteristics and precisely allocate the suitable blocks for different data. The proposed design was evaluated with a series of experiments. The experiment results demonstrate that it could effectively reduce average read response time without significantly increasing the number of total live-page copying compared to the typical wear-leveling strategy.
Subjects
Behavioral sciences | Bit error rate | Computer architecture | data allocation | Flash memories | LDPC soft sensing | Microprocessors | NAND flash memory | Non-volatile memory | Parity check codes | read performance | retention time | Soft sensors
Type
journal article

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