Adaptive Low-Error Fixed-Width Booth Multiplier
Journal
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Journal Volume
E90-A
Journal Issue
6
Pages
1180-1187
Date Issued
2007-06
Author(s)
Abstract
In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65–84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.
Type
journal article