Low Power Design of a Routing-Constrained Scan Architecture
Date Issued
2005
Date
2005
Author(s)
Yu, Zong-en
DOI
en-US
Abstract
以掃描鍊為基礎的測試設計已經廣泛的應用於積體電路以及系統單晶片的設計中，因此降低測試過程中的耗電逐漸變成一個重要的議題。近年來，[15] 中提出了一個低功率掃描鍊設計技術，這項技術有效的降低了耗電以及導線長度。此時，如果能更仔細的考慮權重移轉的觀念，就能得到更好的掃描元件的串接順序。此外，藉由聚落的重新排列，可以讓聚落的順序趨向省電的順序，進而節省耗電。
Scan-based architectures are widely adapted in modern VLSI and SoC testing. Therefore reducing the expensive power consumption in testing procedure has become a primary concern. Recently, a low power scan chain design technique based on clustering and reordering of scan cells is proposed in [15], which effectively reduces the power consumption and the wire length. In this thesis, we improve this technique. With a more precise concern of the notion of weighted transitions, a better way to order scan cells is found. Moreover, a cluster reordering technique is introduced, which is able to find a better order of the clusters, thus reducing the power consumption.
Subjects
掃描鍊
測試設計
低功率
Scan Chain
DFT
Low Power
Type
thesis
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