An 800-MS/s 10b Pipelined ADC with Floating Ring Amplifiers
Part Of
Proceedings - International SoC Design Conference 2024, ISOCC 2024
Start Page
69
End Page
70
ISBN (of the container)
979-835037708-8
Date Issued
2024-08-19
Author(s)
Abstract
This work presents a power-efficient ADC with the hybrid amplifier architecture. Combining the advantages of the ring amplifiers and the floating inverter amplifiers, the proposed amplifier achieves high output swing, wide bandwidth and low power consumption. Fabricated in a 28-nm CMOS technology, a pipelined ADC employs the proposed amplifier to achieve SNDR of 44.34 dB while consuming 11.56 mW from a 0.9-V supply at an 800 MS/s sampling rate.
Event(s)
21st International System-on-Chip Design Conference, ISOCC 2024
SDGs
Publisher
IEEE
Type
conference paper