Low Noise Application of Phase-Locked Loops with Injection-Pulse-Width Calibration and Delta-Sigma Time-to-Digital Converters
Date Issued
2014
Date
2014
Author(s)
Wei, Chih-Lu
Abstract
This thesis consists of two parts. The first part implement a subharmonically injection-locked PLL with a pulse-width-calibrated loop. Subharmonically injection-locked technique is employed to suppress VCO accumulation noise. Besides, we propose an injection-pulse-width calibration technique to discuss the pulse width of injected pulse for the impact on the phase noise. The measure phase noise can achieve better noise performance by the proper pulse width of injected pulse. Moreover, the measured environment at temperature 0~80oC 、supply voltage 1.02~1.18V, the RMS jitter performance also can be improved by the proper pulse width of injected pulse.
The second part implements a Digital PLL with a delta-sigma time-to-digital converter (ΔΣ TDC). We use the oversampling technique to improve the in-band quantization noise of DPLL, and use the feedforward tuning architecture in the controlled path of the digitally-controlled oscillator to reduce the loop latency. Therefore, the phase noise performance is improved. Additionally, the simple first-order delta-sigma modulator architecture also reduce the power and area of TDC. The measured RMS jitter is 861fs. The power consumption and active area of the proposed ΔΣ TDC are 0.519 mW、0.0027mm2 respectively.
Subjects
時脈產生器
Type
thesis
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