Research on Power Combining Technique and Improving Linearity and Back-off Efficiency for CMOS Power Amplifier
Date Issued
2015
Date
2015
Author(s)
Chao, Chun-Yen
Abstract
In this thesis, a K-band modified Doherty power amplifier, a V-band PA using low-frequency IM2 feed-forward method, and a E-band PA using multi-way power combining technique are proposed to improve the back-off efficiency, linearity, and output power of CMOS power amplifiers respectively. First, a K-band modified Doherty power amplifier fabricated in 0.18-μm CMOS technology is proposed to improve the back-off efficiency. The proposed power amplifier consists of two stages for higher gain. The output stage is composed of main and auxiliary paths. The main path consists of common source topology and is biased at class-AB to provide enough gain at small signal. The auxiliary path consists of cascode topology and is biased at class-AB near class B to provide high gain at large signal and to save dc power consumption for small-signal operation. The uneven power splitter and phase-compensation line are used in power splitting to improve the back-off efficiency and OP1dB. According to the measurement results at 22 GHz, the proposed PA provides 13.7-dB small signal gain, 16.3-dBm OP1dB and 17.2-dBm Psat. The peak power-added-efficiency (PAE), PAE at OP1dB, and PAE at 6-dB back-off are 24.8%, 21.5%, and 11.5% respectively. Second, a low-frequency IM2 feed-forward method is used to improve the linearity of the 60 GHz CMOS power amplifier fabricated in 90-nm CMOS technology. The power amplifier consists of two stage for higher gain. The power stage consists of main amplifier and linearizer. The main amplifier consists of cascode topology to provide enough gain. The linearizer consists of two transistors to provide the same magnitude and inverse phase of IM3 current compared to the main amplifier to cancel the IM3 current at the output. The cascode current mirror and DC-level shifter are used to feed the IM2 current in the linearizer. According to the simulation results, the PA provides 15-dB small signal gain, 13.9-dBm OP1dB and 15.2-dBm Psat. The peak PAE and PAE at OP1dB is 13% and 11.5%, respectively. The IM3 signal is reduced about 20 dBc at sweet-spot. According to the measurement results, the dc current of the auxiliary path is different from that of the simulation result. The debug result is provided. Third, a multi-way power combining technique is used to increase the output power of the E-band CMOS power amplifier fabricated in 90-nm CMOS technology. The power amplifier consists of three stage for higher gain. The second and third stages are 16-way and 32-way combining respectively for higher output power. The power combining technique applied in the two stages can simplify the layout of bias circuit and achieve wideband matching. According to the simulation results from 71 to 86 GHz, the PA provides 10~11.8-dB small signal gain, 12.8~13.7-dBm OP1dB and 15.3~16.1-dBm Psat. The peak PAE is 6.8~8%. According to the measurement results, the gain is below 10 dB, and it is different from the simulation. Besides, the input return loss is different from the simulation result. The debug result is provided.
Subjects
mmWave
CMOS
power amplifier
power combining
back-off
efficiency
linearization
Type
thesis
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