Impacts of EOT Scaling of ZrO x /HfO x Dielectric on Monolayer WSe 2 Top-Gate p-MOSFETs
Journal
IEEE Electron Device Letters
Series/Report No.
IEEE Electron Device Letters
Journal Volume
47
Journal Issue
3
Start Page
637
End Page
640
ISSN
0741-3106
1558-0563
Date Issued
2026-01-23
Author(s)
Hsu, Yu-Wei
Lin, Yu-Tung
Chiang, Nien-En
Chen, Shao-Heng
Chiu, Ying-Zhan
Hsu, Chen-Hsun
Wei, Ting-Hua
Lee, Sin-Yue
Su, Zi-Quan
Chiang, Hung-Li
Ni, I-Chih
Lee, Tsung-En
Abstract
This work demonstrates the two-step elevated-temperature atomic layer deposit (ALD) process of bilayer ZrOx/HfOx relatively higher-κ dielectrics reported on chemical vapor deposit (CVD) monolayer (1L) WSe2 for top-gate dielectric. Top-gated 1L-WSe2 pFETs with a low subthreshold swing (S.S. ∼60 mV/dec) are achieved at a low equivalent oxide thickness (EOT) of 0.8 nm. By scaling the physical thickness of this two-step bilayer ZrOx/HfOx dielectric with the pinhole-free AlOx nucleation layer down to 2 nm, the proposed gate stack exhibits a high effective dielectric constant (ϵeff ∼ 14) and strong reliability (breakdown field EBD ∼ 21 MV/cm) at the scaled EOT. This breakthrough in gate dielectric integration on p-type 1L-WSe2 enables balanced n/p performance for 2D-channel devices and enhances the feasibility of future low-power consumption CMOS applications.
Subjects
2D gate stacks
dielectric engineer and low power consumption
effective oxide thickness
monolayer tungsten diselenide
top-gate devices
Two-dimensional material
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article