Session 28 overview: Hybrid ADCs.
Journal
2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017
Pages
464-465
Date Issued
2017
Author(s)
Abstract
Analog-to-digital converters (ADCs) continue to evolve from classical architectures into hybrid converters that combine the strengths of various ADC types. This session demonstrates multiple hybrid ADCs ranging from MHz to GHz bandwidths, employing combinations of SAR, pipeline and oversampling architectures. Pipelined-SAR ADCs utilizing PVT-stabilized dynamic amplifiers, separate comparators per decision and digital amplifiers are disclosed. Noise-shaping phase-domain excess-loop-delay compensation as well as a double noise-shaping quantizer are employed in the ADCs to improve the conversion efficiency.
SDGs
Type
conference paper