PIPELINED SCHEDULE SYNTHESIS FOR MULTIMEDIA SOC
Date Issued
2007
Date
2007
Author(s)
Chih-HsuanWang
DOI
en-US
Abstract
Multimedia SoCs have property of throughput constraints. The throughput of multimedia application is the rate at which it processes input data, and this is usually the prime constraint on most multimedia applications. In order to meet the throughput constraints of these system with low cost, it is necessary to construct more efficient implementation with
pipelined design. Idea of pipelined design is to divide applications into several concurrently executing stages, thus increasing its data rate. In this thesis, we presented a solution to pipelined schedule synthesis for multimedia SoCs such that pipeline buffer is minimized under throughput constraints. We proposed a three-step exploration methodology to obtain pipelined schedule with minimal pipeline buffer which meets the given throughput constraints. Performance evaluation results prove the proposed three-step exploration methodology could reduce the run-time overhead and derive a near-optimal solution.
Subjects
軟硬體共同設計
管線排程
產能限制
多媒體系統晶片
hardware software co-design
pipelined schedule
throughput constraint
multimedia SoC
Type
thesis
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