DFT and ATPG of Two-pattern Tests for Dual-rail Asynchronous Circuits
Date Issued
2015
Date
2015
Author(s)
Wang, Ying-Hsu
Abstract
Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This thesis presents a two-pattern test methodology for dual-rail asynchronous circuits. Our design for testability (DFT) is based on a full-scan, clock-less, Dual-rail scan (DR-scan) technique. To reduce test time, we choose a minimum set of selected test configurations. If there are more than one selected test configuration, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve higher than 92% average test coverage for various asynchronous circuits.
Subjects
Asynchronous circuits
Dual-rail logic
Design for testability
Automatic test pattern generation
Two-pattern tests
Type
thesis
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ntu-104-R02943156-1.pdf
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